To achieve high speed operation of a register file, fast read and write address decodes are essential. Register file decodes are usually done by pre-decoding the addressing lines by ANDing two or more addresses together, then distributing these ANDed lines to the wordline drivers where final decode is done by ANDing again. When the decoded signals are stable, a clock signal then enables the wordline drivers allowing the one wordline driver with the proper decode to activate a DECOUT line to the storage cells of the register file which then either reads or writes the data in the storage cell. Since the speed of the register file is rated in terms of the arrival of the address to the data coming out, the faster the address can be decoded, the faster the register file. The arrival of the addresses are measured relative to a clock signal, which tells the register file that the addresses are now valid and the register file access can now proceed.
FIG. 9 illustrates typical circuitry for implementing address decoders for accessing such register files. The address signals are received by AND circuits 900 for decoding. FIG. 10 illustrates further detail of each AND circuit 900. A clock generator 1001 must distribute clock signals CLK1 and CLK2 throughout the circuit 900, accounting for skew and process variations across the circuit. The first clock signal CLK1 activates the decoding of address signals A1, A2, and A3 by clocked AND circuits 1002 to produce the select signal, which is then received by decode driver circuit 1003 along with another one of the address signals A0. Decode driver 1003 is activated by the second clock signal CLK2 to produce output DECOUT. In circuit 900, it must be guaranteed that clock signal CLK1 rises and there is sufficient time for all select signals to be resolved before the rising of the second clock signal CLK2. Then each of circuits 900 must guarantee that signal CLK2 falls before signal CLK1 falls.
FIGS. 11 and 12 illustrate specific circuit implementations of circuits 1002 and 1003, respectively, using dynamic circuit architecture.
What is needed in the art is an address decoder that does not have the problems associated with the prior art address decoder illustrated in FIGS. 9-12 through its implementation of two separate clock signals.